Real-time index register

ABSTRACT

A counting-register whose enabling signal can be chosen from one of a group of synchronous frequencies for real-time measurement or from an incrementing signal from an iterative loop in a computer. This convertible register comprises two four-bit counters connected in series, an AND gate and a multiplexer to provide an enabling signal at one of the above-stated frequencies to the AND gate which applies the enable signal to the counters if the output from the last of the series counters is a one.

United States Patent [191 Redifer Sept. 16, 1975 [54] REAL-TIME INDEX REGISTER 1668.646 6/1972 Hcmdal 340 1725 3,674,99I 7 1972 I tk t l, .7 235 92 CC 175i Inventor: James Redife" Timonium, 3,824,378 751974 131 .153; 2| 228/48 [73] Assignee: The United States of America as represented by the Secretary of the Primary ExaminerGareth D. Shaw Navy, Washington, DC. Assismnl Examiner-Michael C. Sachs Filed: Jan 1974 Awtto'fig Agent, or F1rmR. S. sciascla; P. Schneider; [2]] App]. No: 435,376

ABSTRACT [52] 340/1725; 235/92 DP; 328/48 A counting-register whose enabling signal can be [51] Int. Cl. H03K 23/09 Chosen from one of a group of Synchronous frequew [58] held of Search 235/92 CC; 328/48 cies for realtime measurement or from an increment- 340/1725 ing signal from an iterative loop in a computer. This convertible register comprises two four-bit counters [56] References cued connected in series, an AND gate and a multiplexer to UNITED STATES PATENTS provide an enabling signal at one of the above-stated 3,094,609 6/1963 Weiss 4. 340/1725 frequencies to the AND gate which applies the enable ,2 l ,7 3 l0/l965 Terzian et al,........ 340/l72.5 signal to the counters if the output from the last of the 3,426,296 2/969 Christiansen et al. 328/48 eries ounters is a One 3,586,835 6/l97l Foch 235/92 CC 3.626.385 l2/l971 Bouman .7 340/l72.5 6 Claims, 2 Drawing Figures l0 l4 coum l 2 COUNT ENABLE TERMINA L 3 ENABLE 4-BlT COUNTER l5 4-B|T COUNTER COUNT O l 2 3 24 4 5 6 i 2 7 INCR l3 2 2 2 2 2 2 3 8 PARALLEL ENABLE 26 TRANSFER BUS CONTROL 22 SIGNAL V PATENIEI] SEP l 8 i975 I4 coum' l6 coum I ENABLE TERMINAL ENABLE 4-an COUNTER '5 v 4-BIT COUNTER coun'r 20 2| 22 23 24 25 26 21 1 INCR '2 I3 I l8 PARALLEL ENABLE 26:4, TRANSFER aus 22 CONTROL SIGNAL r R F IG.

'fi r 32 AND I AND 34 2 0R f3 32 I AND INCREMENT 32 I AND REAL-TIME INDEX REGISTER BACKGROUND OF 'I Hl INVENTION l. Field of Invention This invention relates to counting registers and in particular to frequencyconvertible counting registers to be used with a computerv 2. Description of the Prior Art In prior-art control system that use computers. two problems occur that to date have been handled separately. The are the measurement of time delays (fre uuentlv called real time measurements) and the measuremcnt of iterative ioops. Both of these functions require counterldivider chains. Time-delay measurements generally use a crvstal oscillator or frequency source of one kind or another to count the delay. The output of this counter is then monitored either by a sense line of the computer or an interrupt function so that the computer program may he stopped at the end of an inter\ al.

ltLl'itlhLdtinp are generally using a counter to keep track of the number of passes through the particular iterative-loop calculation. This counter can usually be preset. incremented, and dc tected. when full. completely under program control.

The use of a counter as an index register [iterativeloop counting) was the first to become available in general purpose computers. It essentially grew up" inside the machine. The addition of the real-time clock came later as general computers began to be used in control systems that operated in real time. These clocks were necessary to give the systems proper time syn chronization. These clocks have always been considered a peripheral device and thus have not been incorporated into the actual computer itself.

Since these two functions are performed separately. prior art computers require a number of registers equal to the worst-case index-register load (the largest num her of index registers required at one time] plus the Worst case real tiine cloclcregister load (largest numher of real-time clocks reuuiret'l at one time Thus the number of registers required for a single computer can IIICLISUT'UIIICIIIS I'IILKIC become very large.

SUMMARY OF 'IHF INVENTION The present ilnention alleviates this hardware prolm lem of the prior art b providing a con ertible register which can he timeshare-(l between these two functions.

fhus the restriction of the number of registers to at least the sum of the real-timeclocl-; worst-case load and the indevrcgister worst-case load is eliminated and the new \torst'case design is the maximum sum ofthc real time clocks and the inde\ registers required at an instant of ltltltj.

Briefly. this is accomplished by providing a register that can he used in a computer comprising a counter and circuitry that permits the frequenc at which this counter is enahled to be selected from either a plurality of synchronous frequencies (real-time counting: or an incrementing frequency from an iterative loop in the computerv Thus this register can handle both rcal time and llcl'dlltt. loop counting OBIFCTS OF THE INVhN'IION An obicct of the present in\ cntion is to reduce regis tcr hardvtare in a computer.

A further object of the present imention is to make each countingregistcr more versatile in its use in a sys' tem.

A still further object of the present invention is to re 5 duce the number of registers required in a computer design.

Other objects. advantages and novel features of the present invention will become apparent from the fol lowing detailed description of the invention when considered in conjunction with the accompanying drawings.

BRIEF DESCRIPTION OF THE DRAWINGS FIG. I is a block diagram of one embodiment of the present invention.

FIG. 2 is a block diagram of a multiplexer which can be employed in this invention.

DESCRIPTION OF THE PREFERRED 2U EMBODIMENTS FIG. I shows one embodiment of the present inven' tion. Two fourbit counters I4 and 16 are connected in series. The 931.16 four-hit counter put out by Ad vanced Micro Devices or by Fairchiltl Semiconductors ma he used A count-enahle signal is applied to counter 14 on line I3 from AND gate I2 when both of its inputs are high.

Multiplexer It) generates one of the inputs to the AND gate 12. The multiplexer 10 permits time-sharing of this register among a number of different computer functions. This is done by allowing a choice ol'one front a number of ssnchronous frequencies (realtime measurernent) F F or F or of the increment signal from an iterative loop in the computer to be applied as the multiplexer input to the AND gate I2. A twwbit wordcontrol signal is applied on lines 2t: to the multiplexer II) from the InputlOntput lI 'Oi interface. This control signal determines which ofthe three frequencies F F F or the increment signal will be used as the count enable signal.

The second input to the AND gate I2 is a feedback signal on line 20 from the output of the counter I6. The output of counter 16 is a l at every count until counter I6 is filled. When counter I6 is filled the output is a U. Thus a l is applied to the second input ofthe AND gate 12 until the counter 16 becomes filled. at which point line 20 goes to l and the count'enable signal on line I3 is shut off.

The terminal count on line I8 is generally sensed by an instruction in the computer.

These two counters I4 and 16 can he set to any num her from U to 356 (4 .4 by the transfer bus 22 de pending on the count interval or increment number de sired. The parallel enable signal on line 24 is merely a strobe which is used once the complement of the count desired is set up in the transfenbus lines to count the counters l4 and In to this number. Obviously. any number of counters could be used depending on the count desired as could any length counter.

Aside from the frequency multiplcxing function. this register acts as a normal indes register. It can be loaded in ones complement. incremented. and the terminal count sensed by an instruction.

The only limitation on the utilization of this register is that it may not be used for both functions at the same (iii time.

The basic novelty of this approach is that it allows time-sharing of a register between two functions that require similar hardware but in the past have tradition ally been kept separate.

PK). 2 shows one possible design for multiplexer 10. The control signal on lines 26 is converted into four signals (one line high. the other line high, both high, both low) by block 30. Block 30 is a standard device that is manufactured by a number of electronics firms such as Advanced Micro-Devices or Fairchild Semiconductors. Specifically, a device that may be used for block 30 may be found in the Advanced Micro Devices Data Book" at page 73, part number 93LU9. Block 30 is a standard device labeled 93L09 in the catalogues put out by either Advanced Micro Devices or Fairchild Semiconductors. These four signals are then applied. one to each of a set of four AND gates 32. The other inputs to the four AND gates are F F F and Increment.

One of these four AND gates will be energized by the control signal on line 26 and the frequency applied to that AND gate will be applied to the OR gate 34 which in turn will apply it as the multiplexer input to AND gate 12. Obviously any number of circuits could be developed to perform this multiplexing function.

Obviously, many modifications and variations of the present invention are possible in light of the above teachings. It is therefore to be understood that, within the scope of the appended claims. the invention may be practiced otherwise than as specifically described.

What is claimed is:

l. A real-time index register for use in a computer comprising:

counting means.

multiplexing means for providing an enable signal to step said counting means, said multiplexing means receiving a plurality of simultaneously available, different-frequency signals and one or more incrementing signals from iterative loops in said computer and permitting a selected one of these signals to pass as said enabling signal to said counting means; and

feedback means for applying the output from said counting means to said multiplexing means to en able or disable said multiplexing means from applying said enable signal to said counting means in accordance with the output from said counting means.

2. A rcal-time. index register as in claim 1. wherein said counting means comprises two four-bit counters connected in series.

3. A real-time, index register as in claim 1, wherein the plurality of frequencies which can be used as the enable signal are synchronous frequencies.

4. A real-time index register as in claim 3, wherein said multiplexing means comprises:

a multiplex circuit to which the plurality of frequency signals and the one or more incrementing signals from the computer iterative loops are applied as one set of inputs, and to which a control signal is applied as another input which determines which of the plurality of frequency signals or the one or more incrementing signals will be used as the enable signal; and

gate means to which the enable signal from said multiplex circuit is applied as one input, and to which the signal from said feedback means is applied as the other input to determine whether the enable signal is to be applied to said counting means.

5. A real-time, index register for use in a computer comprising:

counting means;

frequency-generator means for generating a plurality of different-frequency signals simultaneously, each on a different line,

multiplexing means comprising a plurality of gate means, each gate means having applied to one of its inputs either a different increment signal from the iterative loops in said computer or a different frequency signal from said plurality of frequency lines from said frequency-generation means and. at another of its inputs a control signal. the control signal being set to open a selected one of said gate means at the occurrence of a frequency or increment signal so that said frequency or increment signal is applied to step said counting means; and

feedback means for applying the output from said counting means to said multiplexing means to enable or disable said multiplexing means from applying a signal to step said counting means in accordance with the output from said counting means.

6. A real-time, index register as defined in claim 5 wherein said multiplexing means comprises an enable gate to which the counter-stepping signal from said selected one of said gate means is applied as one input, and to which the signal from said feedback means is ap plied as the other input to determine whether this stepping signal is to be applied to said counting means. 

1. A real-time index register for use in a computer comprising: counting means; multiplexing means for providing an enable signal to step said counting means, said multiplexing means receiving a plurality of simultaneously available, different-frequency signals and one or more incrementing signals from iterative loops in said computer and permitting a selected one of these signals to pass as said enabling signal to said counting means; and feedback means for applying the output from said counting means to said multiplexing means to enable or disable said multiplexing means from applying said enable signal to said counting means in accordance with the output from said counting means.
 2. A real-time, index register as in claim 1, wherein said counting means comprises two four-bit counters connected in series.
 3. A real-time, index register as in claim 1, wherein the plurality of frequencies which can be used as the enable signal are synchronous frequencies.
 4. A real-time index register as in claim 3, wherein said multiplexing means comprises: a multiplex circuit to which the plurality of frequency signals and the one or more incrementing signals from the computer iterative loops are applied as one set of inputs, and to which a control signal is applied as another input which determines which of the plurality of frequency signals or the one or more incrementing signals will be used as the enable signal; and gate means to which the enable signal from said multiplex circuit is applied as one input, and to which the signal from said feedback means is applied as the other input to determine whether the enable signal is to be applied to said counting means.
 5. A real-time, index register for use in a computer comprising: counting means; frequency-generator means for generating a plurality of different-frequency signals simultaneously, each on a different line; multiplexing means comprising a plurality of gate means, each gate means having applied to one of its inputs either a different increment signal from the iterative loops in said computer or a different frequency signal from said plurality of frequency lines from said frequency-generation means and, at another of its inputs a control signal, the control signal being set to open a selected one of said gate means at the occurrence of a frequency or increment signal so that said frequency or increment signal is applied to step said counting means; and feedback means for applying the output from said counting means to said multiplexing means to enable or disable said multiplexing means from applying a signal to step said counting means in accordance with the output from said counting means.
 6. A real-time, index register as defined in claim 5 wherein said multiplexing means comprises an enable gate to which the counter-stepping signal from said selected one of said gate means is applied as one input, and to which the signal from said feedback means is applied as the other input to determine whether this stepping signal is to be applied to said counting means. 